The present invention relates to a protocol test device including a network processor.
For the development of protocol test devices which are suitable for building up and operating so-called mobile networks of the third and fourth generation, two fundamental, aspects which partly contradict each other have to be considered:
(1) On the one hand, the complex simulation and emulation scenarios of the higher protocol levels in the fields of terrestrial radio access network and core network of such a network require a vast degree of flexibility and programmability in combination with a high storage capacity and high processor performance. A corresponding flexible and comfortable interface allowing a user to control these scenarios also has to be provided.
(2) On the other hand, however, when linking a protocol test device to the real physical transporting level in mobile networks, the following marginal conditions need to be adhered to:                (i) Several transport network interfaces with high and partly different data rates have to be supported, for example 155 mbit/s in the case of STM-1 and 622 mbit/s in the case of STM-4. In this case, a high number of asynchronous, dynamic links of the user level, which may include language signals and e-mail signals, for example, and of the control level, which may include relaying or switching data for controlling the user level, with complex cells- and/or package-based transport protocols have to be simultaneously included in an individual emulation/simulation scenario.        (ii) Additionally, high demands concerning the real-time behavior (quality of service, qos) of the individual links and the necessity of simulating load cases have to be considered. It has to be considered that the new mobile networks require and specify a clear separation of the control level, i.e. the signalizing/mobility protocol level, and the user level, i.e. the transporting protocol level, so as to allow a separate optimizing and further development of these two worlds. As a result, a fast further development and change in the technologies used, a fast use of new standards and a growth of the range are to be expected on the transporting protocol level.        
At present, the former demands can only be met satisfactorily by using universal processors of the notorious Von-Neumann architecture. Such processors are available at low cost in the off-the-shelf components for various different system/bus concepts, e.g. PC, PCI, cPCI, VME. This type of processor, however, is designed for universal use in a mass market and does not exhibit the relevant performance-critical additional functions for the use in protocol-test devices, for example framing, timing/synchronizing, CRC, CAM. These processors only support standardized interfaces to external components and devices, e.g. a PCI/CPU bus, to memory components etc. Owing to the architecture of these universal processors, due to their high percentage of required memory space and processor performance for the protocol simulation/emulation of the higher protocol levels and the necessary interactions with a transporting network interface via a bus/memory interface, it is absolutely necessary in this case to reduce the effective data exchange to the absolute minimum of significant data.
When accomplishing the above aspects on the basis of such a universal processor, one is faced with the following problems:                It has to be possible to link one or plural physical interfaces with data rates of up to 155/622 mbit/s via the available standard interfaces of the universal processor, by means of a dedicated network interface hardware        Besides the emulation of the transporting network protocols, this interface hardware must be capable of performing two tasks concerning the higher protocol-emulations/simulations performed on the universal processor: on the one hand, the reduction of the data stream from/to the universal processor by performing partial functions of the emulation/simulation of higher protocol levels, for example load simulation, pre-filtering and pre-working of packages concerning information from higher protocols; on the other hand, typical tasks of a protocol-test device, such as the exact generation of sending and receiving triggers, the conduction of error/performance statistics, etc.        In view of protocol standards of the transporting network protocol level which are partially still in the specification phase, ready adaptability of protocol-test devices is not only desired but also a crucial prerequisite to make it possible to react to changes in the standards without major delays and/or without major costs.        Moreover, the development and production of this network interface hardware should be possible at reasonable costs and quickly.        
Two approaches for solving these problems are known in the prior art which both have various major shortcomings:
(1) A first approach relates to the use of one or plural standard hardware components of chip manufacturers from the network field such as specialized interface controllers, transceivers, ASSPs (application specific standard products). With their purpose of use in mind, these components have been designed and developed for a broad mass market with a high number of items and mostly for established transport network technologies. This results in the following relevant disadvantages which prevent a real solution of the above-mentioned problems:                The characteristics or hardware components required for the physical linking with newly developed transport network technologies (e.g. AAL2) only become available at such a late date that their use in protocol test devices is not acceptable since protocol test devices are predominantly required in the early phase of the development and the start of operation of new networks.        These standard hardware components are usually not freely programmable concerning their relevant logic, i.e. concerning firmware or microcode, and thus cannot or only partly realize specific demands in protocol test applications.        The available transfer functions of these components are mostly specialized in special fields of application, for example interworking, switching, voice/video, bulk transfers, with a high number of supported links and typical user-level data profiles; in this, the connection via a standard interface, e.g. a PCI bus, either only plays a minor role or creates a negative load of the overall performance in protocol test scenarios due to inter-processor communication and transmission of irrelevant data.        
With reference to the example of a Motorola C 5 network processor, FIG. 1 illustrates the structure as well as fundamental components of such a network processor. The C 5 exhibits 16 ports 10a through 10p to the physical transport layer of network subscribers. Ports 10a through 10p constitute inputs to as well as outputs from the C 5. Each of the ports 10a through 10p has a topped channel processor 12a through 12p. Each of the channel processors 12a through 12p is bi-directionally connected to a ring bus 14, a payload bus 16 as well as a global bus 18. The channel processors 12a through 12p analyze input serial data streams from one or plural physical interfaces, perform corresponding search algorithms for incoming packages as well as, if necessary, later modifications or conversions and transmit the resulting data stream to one or plural output channel processors (“forwarding”). This way of functioning corresponds to a logical flat in-stream processing.
The C 5 is a single-chip system with high functional integration. This network processor exhibits 16 freely programmable multi-purpose CPUs as well as 5 co-processors with an aggregated entire processing performance of approx. 3,000 MIPS. Every 4 of said multi-purpose CPUs may be linked to form one cluster which will allow a flexible increase of the processing performance as well as of the amount of the protocol functions to be realized via aggregation of the instruction memories. The co-processors perform necessary typical tasks in network applications such as queuing, buffer service and complex search algorithms. All processors within the C 5 are linked via said three high-speed bus systems and have a total bandwidth of approx. 16 gbps.
In view of the purpose of use of such a network processor 8, various components, amongst others the co-processors, are likewise linked to one or plural of the buses. A buffer management unit 20 as well as a queue management unit 22 are linked to global bus 18 and payload bus 16. A fabric processor 24 which is connected to topped processing units 25, as well as an executive processor 26 are linked to the ring bus 14, the payload bus 16 as well as the global bus 18. A table-lookup unit 28 is linked to the ring bus 14.
FIG. 2 shows the general way of functioning and the typical area of use of a network processor 8. This network processor 8 is linked to physical transport layers 30a through 30p of network subscribers via its ports 10a through 10p. If necessary, an interface circuit may be inserted. Of course, it is also possible to link only part of said ports 10a through 10p to network subscribers. A control unit 32, which is connected to said network processor 8 via a standardized interface 34, for example a PCI bus, allows a user to configure the network processor 8 with respect to its tasks, which typically include the following: switching, routing, package classification, quality of service applications, package modifications, bandwidth aggregation, interworking applications, cell-, package conversion, data framing, data formatting, billing and remote monitoring. One aspect common to all fields of use is that the network processor 8 operates in-stream, i.e. as a switching center within a network. This is illustrated in FIG. 2 in that the network processor 8, as indicated by arrow 36, switches signals between port 10a and port 10p. However, it may also be envisaged, as illustrated by arrows 38a and 38b, to forward the data streams to a topped switching center 42 via a non-standardized interface 40, which switching center 42 then in turn performs switching tasks, as indicated by arrows 44a through 44d. The intended area of use of network processors is thus switchboard and interworking units within one network.
(2) A second approach provides for the realization of transport interface hardware by the use of FPGAs (field programmable gate arrays) and/or ASICs (application specific integrated circuits) which creates a solution that is adapted to the above demands, in particular an acceptable compromise between the programmability of a software-based design and a performance-optimized processing via functions which are realized in hardware form. The disadvantages of such a solution, however, are its high costs and the long development phase, combined with the prerequisite of a consolidation concerning the transporting network protocols which are to be supported.
Consequently, neither prior art approach presents an acceptable solution for the above mentioned problems. Therefore it is the object of the present invention to provide a protocol test device which allows inexpensive testing of mobile networks of the third and fourth generation.